In order for an electronic system to operate properly and reliably, the timing specifications of each integrated circuit in the system must be considered and guaranteed. To assist in the design of electronic systems, manufacturers of semiconductor devices categorize their integrated circuits by speed grade, which designates the preferred speed for proper operation. For example, memory devices of conventional microprocessor-based systems may be designated to operate at various speed grades, such as, 66 MHZ or 100 MHZ. Higher speed grade devices are typically sold at a higher price than lower speed grade devices.
Typically, a manufacturer of semiconductor devices tests each integrated circuit as it is produced. If the integrated circuit passes the timing requirements for the targeted speed grade, it is sold at the corresponding price. If the integrated circuit fails, it may be down-graded to a lower speed grade and sold for a lower price. For example, if a memory device fails the timing requirements for operation in a 100 MHZ bus system, it may be downgraded to a lower speed grade for operation in a 66 MHZ bus system and sold at a price lower than the initial target price.
In order to meet the requirements of a particular speed grade, the integrated circuit must meet several different timing specifications. For example, consider a conventional system where a transmitting device is connected to a receiving device by a common bus and the communication between the devices is controlled by a common external clock. For proper communication, it is critical that the transmitting device provide its data to the receiving device no later than a specified time after the previous rising edge of the clock signal. This specified time allows the inputs of the receiving device to stabilize before the next rising edge of the clock when the data is latched by the receiving device. This requirement is known as the output access time of the transmitting device. In order for an integrated circuit to be cataloged at a particular speed grade, the output access time of the integrated circuit must be no greater than output access time specified for that speed grade.
Similarly, the transmitting device must continue to provide the data to the receiving device for a specified time after the rising edge of the clock signal. This requirement, known as the output hold time, ensures that the receiving device has completely latched the communicated data before the transmitting device removes the data from the bus. Therefore, in addition to satisfying the output access time requirement, the output hold time of the transmitting device must be no less than the output hold time required for the speed grade.
Thus, it is possible for an integrated circuit to fail a particular timing specification, such as the output access time, yet meet the other timing specifications such as the output hold time. In some situations, an integrated circuit cannot be sold at the targeted speed grade because it failed the access time requirement and it may not be downgraded because its hold time is too short for operation at the lower speed grade. In this situation, the integrated circuit may not be sold at either speed grade and the manufacturer incurs a loss.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an apparatus and method for configuring the timing characteristics of an integrated circuit. There is a need in the art for an integrated circuit which, in the event the integrated circuit fails the timing specifications of the desired speed grade, may be configured to meet the timing specifications of a lower speed grade.